It is known from published patent specification WO98/05935A1 that sensors can be placed on a substrate in such a way that the sensor elements are positioned over an opening in the substrate. It is known from published patent specification JP 2000195827A as well as in the quotation in Patent Abstracts of Japan to place grooves on one side of a substrate, and in order to separate the LED components formed on a wafer to make incisions from the back side of the substrate over the grooves to such a depth that the grooves are opened. In the case of two connected substrates, it is known from published patent specification JP09223678A that the procedure is to remove cutouts from a second substrate to separate the components.
Examples of components that are realized in two connected substrates are so-called COC (chip on chip) components which have a type of vertical integration. The two substrates which both component structures can have are interconnected through two main surfaces, while at the same time, if necessary, an electrical contact can be established between component structures in different substrates. The component can have common or separate electrical contacts for both connected substrates. If there are electrical contacts on both substrates, the mutual electrical connection of the component structures realized in the two substrates can also be made by bonding wires between the respective contacts.
The COC technology is employed for component encapsulation at the chip level, also known as “first level packaging”. It is also used where further miniaturization of the components is desired, and where components with less need for space on a circuit board or in a module are sought. The technology is used in particular to produce ICs, micromechanical components or sensors (MEMS), as well as for producing micro-optical components.
The substrates of the COC components are usually produced by integrated methods at the wafer level, and the two component substrates are also connected at the wafer level. It is therefore necessary, on the lower of the two substrates, or in the case of a larger number of substrates, on a lower substrate, to expose the electrical terminal pads after the two substrates have been connected, and, for example, to produce a window in the top substrate. If the window is produced after the two substrates are connected, there is a danger that the process of opening the window to expose the contacts (terminal pads) will cause the latter or other structures on the lower of the two substrates to be damaged or even destroyed.
It is therefore known and usual to form the windows in which the terminal pads are exposed in the upper one of the two wafers before the substrates are connected. In the case of semiconductor wafers, that can be done for example by anisotropic etching from one or two sides of the top wafer. As the etching technique, it is possible for example to employ reactive ion etching. However, a disadvantage of the method is that the top substrate is weakened as a result of the pre-produced window, possible breaking points are already predefined as with the windows. This is disadvantageous for the joining of the two wafers, which takes place in particular under pressure. The result of this is that COC technology, in which two substrates are joined together by bonding, is limited at the wafer level to wafers with a diameter of four to a maximum of six inches.
An additional disadvantage of this method is that precisely located etch-through of the windows requires a great expenditure of time and processing.